A continuous-time sigma-delta analog-to-digital converter (continuous-time sigma-delta ADC) differs from a discrete-time sigma-delta ADC in that the continuous-time sigma-delta ADC makes use of a loop filter while the discrete-time sigma-delta ADC uses a switched-capacitor filter, which may require the use of fast settling circuits and an input buffer to eliminate sample glitches. The switched-capacitor filter may limit the signal bandwidth. Additionally, due to the thermal noise of the capacitors used in the switched-capacitor filters, large capacitors may be needed to obtain good signal-to-noise ratios.
The loop filter may have a topology that is active-Gm-C, active-RC, a combination of active-Gm-C and active-RC, or a combination of active and passive networks. A diagram shown in FIG. 1 illustrates a view of a typical prior art continuous-time sigma-delta ADC 100. The continuous-time sigma-delta ADC 100 includes an input RC network 105 and an active-passive Gm-C/Quantizer/DAC circuit (GQD) 110.
The RC network 105, which may provide passive filtering of the input signals to the continuous-time sigma-delta ADC, may include resistors (R), such as resistors 155 and 156, and capacitors (C), such as capacitors 160 and 161, for the positive and negative signal inputs to the continuous-time sigma-delta ADC 100. The GQD 110 may include a loop filter 170, a quantizer 175, and a feedback loop 180 from a positive and a negative output from the quantizer 175 back to the positive and the negative inputs to the loop filter 170. Summing points combine the signal from the respective feedback loop 180 and the respective input signal and provides it to the loop filter 170. The GQD 110 may evaluate an input signal (provided by the RC network 105), measure an error signal present in the input signal, and provide compensation for the error signal. During normal operation of the GQD 110, a virtual short circuit may be maintained between the positive and the negative inputs of the loop filter 170 due to the GQD's high gain and its negative feedback loop. The feedback loop 180 may include a digital-to-analog converter (DAC) 185 to provide an analog version of the feedback of the quantizer 175 output.
Due to the nature of the GQD 110, the input common mode level of the loop filter 170 may be identical to the common mode level of the input signal. However, if the input signal is to be provided by a separate integrated circuit (for example, an RF chip coupled to the continuous-time sigma-delta ADC 100), the common mode signal levels at the input to the continuous-time sigma-delta ADC 100 could be too high or too low for proper operation and reliability. Therefore, there may be a need to accommodate different common mode levels at the input to the continuous-time sigma-delta ADC 100 to enable reliable and optimal operation between the continuous-time sigma-delta ADC 100 and a variety of RF chips. The common mode level may be higher than a supply voltage of the loop filter 170 in the GQD 110.
If the continuous-time sigma-delta ADC 100 is fabricated using a low-voltage process, reliability issues may arise due to the high common mode level. Even with acceptable common mode levels, during start-up, overload conditions, or power supply loss, when the GQD 110 loop may be incapable of maintaining the summing junction (at the input to the loop filter 170, for example) at the common mode level, the differential swing of the input signal appears at the summing junction and may cause a degradation in the reliability of the continuous-time sigma-delta ADC 100.